This application makes reference to and claims all benefits accruing under 35 U.S.C. Section 119 from an application entitled, xe2x80x9cMethod of Fabricating Nickel Etching Mask,xe2x80x9d filed in the Korean Industrial Property Office on Jul. 18, 2000 and there duly assigned Ser. No. 2000-40909.
1. Field of the Invention
The present invention relates generally to a light waveguide fabrication method, and in particular, to a method of fabricating a nickel etching mask by plating for manufacture of a silica PLC (Planar Lightwave Circuit).
2. Description of the Related Art
Many studies have recently been focused on optical integration technology, and more particularly, to a method of manufacturing optical waveguide chip, which contain one or more planar waveguides, or known as Planar Lightwave Circuits. PLCs are used as optical components for the purpose of optical signal processing, such as modulation, switching, and multiplexing of optical signals. The production of optical waveguides device involves designing, manufacture, and packaging of the optical waveguides. Optical fibers are connected to the planar optical waveguides to function as an optical component in an optical communication system. To this end, an optical waveguide is an optical transmission line keeping light waves and propagating them with low loss. The optical waveguide is comprised of a core with a high refractive index and a cladding with a low refractive index surrounding the core. As such, optical fibers connected to the planar optical waveguides formed in the PLC serves as Arrayed Waveguide Gratings (AWGs) and thermal optical switches. A metal mask is usually used to fabricate a PLC for an optical communication module. Basically, the metal mask is formed by sputtering of a metal layer, photoresist patterning, and dry etching operations.
FIGS. 1A to 1G are cross-sectional views illustrating the conventional metal etching mask fabrication method for use in the manufacturing of a PLC.
FIG. 1A illustrates the step of depositing chrome on a silica layer 10, which is formed by depositing silica (SiO2) on silicon (Si), by sputtering process. A chrome seed layer 12 is formed to a thickness of tens of nanometers (nm) on a substrate 10. FIG. 1B illustrates the step of depositing gold on the chrome seed layer 12 by sputtering process. The thickness of a gold seed layer 14 is the tens of nanometers. FIG. 1C illustrates the step of forming a photoresist layer 16 to be relatively thick on the chrome seed layer 12. FIG. 1D illustrates the step of patterning the photoresist layer 16 by photolithography. FIG. 1E illustrates the step of forming a nickel layer 18 by plating nickel on photoresist patterns 17. The nickel layer 18 grows selectively only on conductive portions. FIG. 1F illustrates the step of removing the photoresist patterns 17 using acetone. FIG. 1G illustrates the step of removing the gold seed layer 14 by wet etching, as well as the chrome seed layer 12 by dry etching.
The nickel layer 18 exhibits low electrical conductivity and low thermal conductivity with the substrate 10. Therefore, it is difficult to use the nickel layer 18 as a seed layer. Instead, a chrome layer 12 with high electrical conductivity, in addition to high thermal conductivity, 10 is preferably to be used as a seed layer. In addition, when nickel layer 18 is plated on the chrome seed layer 12, the surface between the nickel layer 18 and the chrome seed layer 12 exhibits low conductivity. To solve this problem, the gold layer 14 having high junction characteristics with both the chrome and the nickel is interposed between the nickel layer 18 and the chrome layer 12. As a result, the use of the different seed layers (i.e., the chrome layer 12 and the gold layer 12) makes the fabrication process more complexity as a separate requirement of dry etching and wet etching is required in the conventional etching mask fabrication method.
Deposition of the two seed layers and particularly, different removal operation of the seed layers after plating process complicates the operation and increases the processing time. The process is more cumbersome as the gold layer 14 may require cleansing when isotropically etched by wet etching. Furthermore, because the barrel etcher provides a purely isotropic etch as shown in FIG. 1D, there is poor dimensional control when etching a number of photoresist bodies in an array due to the so-called xe2x80x9cbulls-eyexe2x80x9d effect in which structures at the edges of array are etched more rapidly than the structure towards the center of the array. Hence, the xe2x80x9cbull""s-eyexe2x80x9d effect during the dry etching process may change the line widths of patterns across the substrate.
It is, therefore, the present invention relates to a method of fabricating an etching mask with nickel plated on a chrome seed layer and a nickel seed layer.
It is another aspect of the present invention is to provide a nickel etching mask fabrication method for simplifying processing.
It is a further aspect of the present invention is to provide a nickel etching mask fabrication method for minimizing the possibility of contamination.
The foregoing and other objects can be achieved by providing a metal etching mask fabrication method. Chrome is first sputtered on a silica layer and a photoresist is deposited to be thick on the chrome layer. The photoresist layer is patterned, first nickel is sputtered on the photoresist pattern layer, and a second nickel layer is formed on the first nickel layer by electroplating. The photoresist pattern layer and the first nickel layer formed on the photoresist pattern layer are removed using acetone, and the chrome layer is removed by dry etching in plasma using a gas.